Direct Optimization of a PCI Express Link Equalization in Industrial Post-Silicon Validation

Post-silicon validation is a crucial industrial testing process in modern computer platforms. Post-silicon validation of high-speed input/output (HSIO) links can be critical for making a product release qualification. Peripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry, and one of the most complex HSIO interfaces. PCIe data rates increase on every new generation. To mitigate channel effects due to the increase in transmission speeds, the PCIe specification defines requirements to perform equalization (EQ) at the transmitter (Tx) and at the receiver (Rx). During the EQ process, one combination of Tx/Rx EQ coefficients must be selected to meet the performance requirements of the system. Testing all possible coefficient combinations is prohibitive. Current industrial practice consists of finding a subset of combinations at post-silicon validation using maps of EQ coefficients, which are obtained by measuring the eye height, eye width, and the eye asymmetries of the received signal. Given the large number of electrical parameters and the multiplicity of signal eyes that are produced by on-die probes for observation, finding this subset of coefficients is often a challenge. In order to overcome this problem, a direct optimization method based on a suitable objective function formulation to efficiently tune the Tx and Rx EQ coefficients to successfully comply with the PCIe specification is presented in this report. The proposed optimization approach is based on a low-cost computational procedure combining pattern search and Nelder-Mead methods to efficiently solve an objective function with many local minima, and evaluated by lab measurements on a realistic industrial post-silicon validation platform

High-Speed Links Receiver Optimization in Post-Silicon Validation Exploiting Broyden-based Input Space Mapping

One of the major challenges in high-speed input/output (HSIO) links electrical validation is the physical layer (PHY) tuning process. Equalization techniques are employed to cancel any undesired effect. Typical industrial practices require massive lab measurements, making the equalization process very time consuming. In this paper, we exploit the Broyden-based input space mapping (SM) algorithm to efficiently optimize the PHY tuning receiver (Rx) equalizer settings for a SATA Gen 3 channel topology. We use a good-enough surrogate model as the coarse model, and an industrial post-silicon validation physical platform as the fine model. A map between the coarse and the fine model Rx equalizer settings is implicitly built, yielding an accelerated SM-based optimization of the PHY tuning process

A Holistic Methodology for System Margining and Jitter Tolerance Optimization in Post-Silicon Validation

The optimization of receiver analog circuitry in modern high-speed input/output (HSIO) links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose an innovative objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-Si validation time

Jitter Tolerance Acceleration Using the Golden Section Optimization Technique

Post-silicon validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of computer platforms under the current time-to-market (TTM) commitments. The goal of post-silicon validation for HSIO links is to confirm design robustness of both receiver (Rx) and transmitter (Tx) circuitry in a real application environment. One of the most common ways to evaluate the performance of a HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) through the link under worst stressing conditions. However, JTOL testing is very time-consuming when executing at specification BER, and the testing time is extremely increased when considering manufacturing process, voltage, and temperature (PVT) test coverage for a qualification decision. In order to speed up this process, we propose a new approach for JTOL testing based on the golden section algorithm. The proposed method takes advantage of the fast execution of the golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are seen. Our proposed methodology is validated by implementing it in a server HSIO link

Direct Optimization of a PCI Express Link Equalization in Industrial Post-Silicon Validation (poster)

Post-silicon validation is a crucial industrial testing process in modern computer platforms. Post-silicon validation of high-speed input/output (HSIO) links can be critical for making a product release qualification. Peripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry, and one of the most complex HSIO interfaces. PCIe data rates increase on every new generation. To mitigate channel effects due to the increase in transmission speeds, the PCIe specification defines requirements to perform equalization (EQ) at the transmitter (Tx) and at the receiver (Rx). During the EQ process, one combination of Tx/Rx EQ coefficients must be selected to meet the performance requirements of the system. Testing all possible coefficient combinations is prohibitive. Current industrial practice consists of finding a subset of combinations at post-silicon validation using maps of EQ coefficients, which are obtained by measuring the eye height, eye width, and the eye asymmetries of the received signal. Given the large number of electrical parameters and the multiplicity of signal eyes that are produced by on-die probes for observation, finding this subset of coefficients is often a challenge. In order to overcome this problem, a direct optimization method based on a suitable objective function formulation to efficiently tune the Tx and Rx EQ coefficients to successfully comply with the PCIe specification is presented in this report. The proposed optimization approach is based on a low-cost computational procedure combining pattern search and Nelder-Mead methods to efficiently solve an objective function with many local minima, and evaluated by lab measurements on a realistic industrial post-silicon validation platform

Fast jitter tolerance testing for high-speed serial links in post-silicon validation

Post-silicon electrical validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of high-performance computer platforms under current aggressive time-to-market (TTM) commitments. Improvements in signaling methods, circuits, and process technologies have allowed HSIO data rates to scale well beyond 10 Gb/s. Noise and EM effects can create multiple signal integrity problems, which are aggravated by continuously faster bus technologies. The goal of post-silicon validation for HSIO links is to ensure design robustness of both receiver (Rx) and transmitter (Tx) circuitry in real system environments. One of the most common ways to evaluate the performance of a HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) of the link under worst stressing conditions. However, JTOL testing is extremely time-consuming when executed at specification BER considering manufacturing process, voltage, and temperature (PVT) test coverage. In order to significantly accelerate this process, we propose a novel approach for JTOL testing based on an efficient direct search optimization methodology. Our approach exploits the fast execution of a modified golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are found. Our proposed methodology is validated in a realistic industrial server post-silicon validation platform for three different computer HSIO links: SATA, USB3, and PCIe3.ITESO, A.C

A Multi-Stage CTLE Design and Optimization for PCI Express Gen6.0 Link Equalization

The continuously increasing bandwidth demand from new applications has led to the development of the new peripheral component interconnect express (PCIe) Gen6, reaching data rates of 64 giga-transfers per second (GT/s) and adopting the pulse amplitude modulation 4-level (PAM4) signaling scheme. While PAM4 solves the bandwidth requirements, it brings new challenges for the physical channel design. PAM4 is more susceptible to errors due to various noise sources caused by reduced voltage (and timing) ranges, yielding a higher bit error rate (BER). It also introduces new challenges in slicers, transition jitter, and equalizers, making of equalization (EQ) a critical process for PAM4 signaling. In this paper, we propose a multi-stage continuous-time linear equalizer (CTLE) with high-band, mid-band, and low-band frequency boost stages to deal with highly lossy channels. Given the complexity of EQ of multi-level signals, optimization techniques are used, including an efficient optimization of the transmitter finite impulse response (FIR) filter and the receiver CTLE tuning.ITESO, A.C

PCIe Gen5 Physical Layer Equalization Tuning by Using K-means Clustering and Gaussian Process Regression Modeling in Industrial Post-silicon Validation

Peripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry. The continuously increasing bandwidth demand from new applications has led to the development of the PCIe Gen5, reaching data rates of 32 GT/s. To mitigate undesired channel effects due to such high-speed, the PCIe specification defines an equalization process at the transmitter (Tx) and the receiver (Rx). Current post-silicon validation practices consist of finding an optimal subset of Tx and Rx coefficients by measuring the eye diagrams across different channels. However, these experiments are very time consuming since they require massive lab measurements. In this paper, we use a K-means approach to cluster all available post-silicon data from different channels and feed those clusters to a Gaussian process regression (GPR)-based metamodel for each channel. We then perform a surrogate-based optimization to obtain the optimal tuning settings for the specific channels. Our methodology is validated by measurements of the functional eye diagram of an industrial computer platform.ITESO, A.C

Post-silicon Receiver Equalization Metamodeling by Artificial Neural Networks

As microprocessor design scales to the 10 nm technology and beyond, traditional pre- and post-silicon validation techniques are unsuitable to get a full system functional coverage. Physical complexity and extreme technology process variations severely limits the effectiveness and reliability of pre-silicon validation techniques. This scenario imposes the need of sophisticated post-silicon validation approaches to consider complex electromagnetic phenomena and large manufacturing fluctuations observed in actual physical platforms. One of the major challenges in electrical validation of high-speed input/output (HSIO) links in modern computer platforms lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel undesired effects induced by the channels. Current industrial practices for PHY tuning in HSIO links are very time consuming since they require massive lab measurements. An alternative is to use machine learning techniques to model the PHY, and then perform equalization using the resultant surrogate model. In this paper, a metamodeling approach based on neural networks is proposed to efficiently simulate the effects of a receiver equalizer PHY tuning settings. We use several design of experiments techniques to find a neural model capable of approximating the real system behavior without requiring a large amount of actual measurements. We evaluate the models performance by comparing with measured responses on a real server HSIO link

Design and baseline characteristics of the finerenone in reducing cardiovascular mortality and morbidity in diabetic kidney disease trial

Background: Among people with diabetes, those with kidney disease have exceptionally high rates of cardiovascular (CV) morbidity and mortality and progression of their underlying kidney disease. Finerenone is a novel, nonsteroidal, selective mineralocorticoid receptor antagonist that has shown to reduce albuminuria in type 2 diabetes (T2D) patients with chronic kidney disease (CKD) while revealing only a low risk of hyperkalemia. However, the effect of finerenone on CV and renal outcomes has not yet been investigated in long-term trials. Patients and Methods: The Finerenone in Reducing CV Mortality and Morbidity in Diabetic Kidney Disease (FIGARO-DKD) trial aims to assess the efficacy and safety of finerenone compared to placebo at reducing clinically important CV and renal outcomes in T2D patients with CKD. FIGARO-DKD is a randomized, double-blind, placebo-controlled, parallel-group, event-driven trial running in 47 countries with an expected duration of approximately 6 years. FIGARO-DKD randomized 7,437 patients with an estimated glomerular filtration rate >= 25 mL/min/1.73 m(2) and albuminuria (urinary albumin-to-creatinine ratio >= 30 to <= 5,000 mg/g). The study has at least 90% power to detect a 20% reduction in the risk of the primary outcome (overall two-sided significance level alpha = 0.05), the composite of time to first occurrence of CV death, nonfatal myocardial infarction, nonfatal stroke, or hospitalization for heart failure. Conclusions: FIGARO-DKD will determine whether an optimally treated cohort of T2D patients with CKD at high risk of CV and renal events will experience cardiorenal benefits with the addition of finerenone to their treatment regimen. Trial Registration: EudraCT number: 2015-000950-39; ClinicalTrials.gov identifier: NCT02545049